In general, semiconductor (microelectronic) devices can include an active region in which unit devices are formed, and a device isolation region that defines the unit devices. The device isolation region accounts for a large proportion of a total area of semiconductor devices, and thus miniaturization of the device isolation region may be desired for high integration of semiconductor devices. In addition, in order to ensure that devices properly operate, a device isolation region should have a structure that can reduce or prevent interference between devices and decrease junction capacitance. In the past, Local Oxidation of Silicon (LOCOS) type oxide layers were used as a device isolation layer of semiconductor devices. Moreover, shallow trench isolation (STI) type device isolation layers that have a narrow width and can have excellent device isolation properties are widely used.
FIG. 1 is a schematic cross-sectional view of a semiconductor device including a conventional STI-type device isolation layer.
Referring to FIG. 1, device isolation layers 2 are formed in a substrate 1. An active region 3 including a source/drain region and a channel region is formed between the device isolation layers 2, and a gate structure 9 is formed on the active region 3. Such device isolation layers 2 are filled with insulating material, and thus electrically separate the devices from each other. In detail, as illustrated in FIG. 1, a silicon oxide layer 4 and a silicon nitride layer 6 may be formed on inner walls of the device isolation layer 2. And then, the device isolation layer 2 is filled with a buried layer 8 having a gap fill material such as spin-on-glass (SOG).
However, the silicon nitride layer 6 may trap electrons (e−), and thus electrons are trapped at an interface between the silicon oxide layer 4 and the silicon nitride layer 6. Accordingly, holes (h+) are concentrated in a region of the substrate 1 adjacent to the device isolation layer 2 due to the trapped electrons. This is referred to as hot electron induced punch-through (HEIP). Due to the HEIP, current may flow even when a voltage is not applied to a gate 9, and thus a threshold voltage may decrease and leakage current may increase, resulting in defective devices. Such a HEIP phenomenon may be especially problematic in a p-channel metal-oxide-semiconductor (p-MOS) device in which holes are the majority carrier and Vpp is applied at a high voltage, and in particular, off-current characteristics may be degraded. To address these problems, methods of increasing the thickness of a silicon oxide layer in order to reduce or prevent electrons from becoming trapped in a silicon nitride layer have been proposed. However, there may be limits on forming of the silicon oxide layer having a large thickness, which can reduce a gap fill margin of device isolation layers of a cell region, particularly.